Zhenyu Bai
Currently post-doc @ NUS.
I am a researcher specializing in computer architecture and compiler techniques, currently focusing on reconfigurable dataflow architectures.
Publications
- 2024
- Li, Z., Yin, C., Bandara, T. K., Juneja, R., Tan, C., Bai, Z., & Mitra, T. (2024). Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning. arXiv preprint arXiv:2412.08137.
- Li, H., Li, Z., Bai, Z., & Mitra, T. (2024). ASADI: Accelerating Sparse Attention Using Diagonal-based In-Situ Computing. In 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (pp. 774–787).
- Bai, Z., Dangi, P., Li, H., & Mitra, T. (2024). SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs. Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC).
- Yan, Z., Bai, Z., Mitra, T., & Wong, W.F. (2024). SparrowSNN: A Hardware/software Co-design for Energy Efficient ECG Classification. arXiv preprint arXiv:2406.06543.
- Dangi, P., Bai, Z., Juneja, R., Wijerathne, D., & Mitra, T. (2024). ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML. Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques (PACT)
- Yan, Z., Bai, Z., & Wong, W.F. (2024). Reconsidering the energy efficiency of spiking neural networks. arXiv preprint arXiv:2409.08290.
- 2023
- Bai, Z., Cassé, H., Carle, T., & Rochange, C. (2023). Computing execution times with execution decision diagrams in the presence of out-of-order resources. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(11), 3665–3678.
- Bai, Z. (2023). Modélisation du comportement temporel du pipeline pour le calcul de WCET. (Doctoral dissertation, Université Paul Sabatier-Toulouse III).
- 2022
- Bai, Z., Cassé, H., De Michiel, M., Carle, T., & Rochange, C. (2022). A framework for calculating WCET based on execution decision diagrams. ACM Transactions on Embedded Computing Systems (TECS), 21(3), 1–26.
- 2021
- Bai, Z., Cassé, H., Michiel, M., Carle, T., & Rochange, C. (2021). Déterminer le WCET d'applications temps-réel en présence de latences d'exécution variables. In Conférence francophone d'informatique en Parallélisme, Architecture et Systeme (COMPAS 2021).
- 2020
- Bai, Z., Casse, H., De Michiel, M., Carle, T., & Rochange, C. (2020). Improving the performance of WCET analysis in the presence of variable latencies. In The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (pp. 119–130).
- 2019
- Bai, Z., Monniaux, D., & Maïza, C. (2019). PLRU Cache Analysis. In The Junior Researcher Workshop on Real-Time Computing.